1. Technical Field
The present invention relates to phase locked loops, and more particularly to selective phase rotation in a phase locked loop used for clock generation, such as for clocks in microelectronic circuitry.
2. Description of the Related Art
Phase locked loops ("PLL's") are useful for generating clock signals, such as for clocks used in microelectronic circuitry, including microprocessors. However, conventional PLL's are susceptible to noise. Furthermore, power supplies, particularly for microprocessors, can be very noisy, resulting in unacceptable jitter in the output signal of a PLL. This jitter is even more problematic for the multi-phase clocks used in microprocessors.
A method and apparatus useful for generating a clock signal, which is less susceptible to noise than conventional PLL's, has been disclosed in one or more of the above referenced patent applications, according to which a set of signals are generated having a predetermined phase relation to one another. The clock is sourced by a signal successively switched from one of the signals in the set to another (i.e., "rotated"), with the effect that the clock source signal is phase rotated. In this context, at least, there is needed a method and apparatus for selective phase rotation of a signal in a phase locked loop.